Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and particularly to a power semiconductor device and a method of manufacturing the same.
Description of the Background Art
A vertical structure of a power semiconductor device in which a current flows from a side of a main surface of a substrate toward a back surface of the substrate is the mainstream. A vertical metal oxide semiconductor field effect transistor (MOSFET) represents such a power semiconductor device having a vertical structure.
A vertical trench gate type MOSFET has an n-type drain region formed on a back surface of a substrate, an n-type drift region formed on an n-type drain, a p-type base region formed in the n-type drift region, an n-type source region formed in the p-type base region and at a main surface of the substrate, and a gate electrode opposed to the p-type base region with a gate insulating film being interposed. A trench formed in the main surface of the substrate is filled with the gate electrode.
A method of implanting ions in three stages with an implantation depth being varied and thereafter performing heat treatment is available as a method of forming such a p-type base region (for example, Japanese Patent Laying-Open No. 2012-253276).